1. Technical Field
The present invention relates in general to cache controllers in data processing systems and in particular to cache controllers which layer cache and architectural specific functions. Still more particularly, the present invention relates to layering cache and architectural specific functions within a cache controller to permit complex operations to be split into cache and architectural operations.
2. Description of the Related Art
Data processing systems which utilize a level two (L2) cache typically include a cache controller for managing transactions affecting the cache. Such cache controllers are conventionally implemented on a functional level, as depicted in FIG. 4. For example, a cache controller 402 may include logic 404 for maintaining the cache directory, logic 406 for implementing a least recently used (LRU) replacement policy, logic for managing reload buffers 408, and logic for managing store-back buffers 410. In traditional implementations, the cache is generally very visible to these and other architectural functions typically required for cache controllers, with the result that cache controller designs are specific to a particular processors such as the PowerPC.TM., Alpha.TM., or the x86 family of processors.
Operations supported by the basic cache controller design depicted in FIG. 4 may be simple or complex. Simple operations convey a single piece of information, while complex operations contain more than one distinct piece of information. Compare, for example, the READ and READ atomic operations supported by the PowerPC.TM. architecture. The READ operation simply conveys that a given memory location should be read. The READ atomic operation conveys that a specific memory locations should be read, and that the processor initiating the operation should be informed if any other device in the hierarchy changes the data in the memory location. The READ atomic operation is used for synchronization.
To the extent complex operations supported by a given architecture cannot be split, controller logic for supporting that operation must remain interdependent, Often the logic for a complex operations is an intricate state machine supporting a variety of special cases for the operation. Such logic is complex, requires significant silicon area to implement, and is difficult to interlock with other logic supporting other operations.
It would be desirable, therefore, to be able to split complex operations for simplification of the logic supporting the operation. It would further be desirable to split complex operations to increase the speed of their performance by implementing faster logic for performing the operations.